Application-specific integrated circuit

Results: 654



#Item
61HES-DVM™ HW/SW Validation Platform  Hybrid Verification Platform HES-DVMTM is a Hybrid Verification and Validation Platform for Hardware and Software developers of SoC and ASIC designs up to 144M ASIC gates. Utilizing

HES-DVM™ HW/SW Validation Platform Hybrid Verification Platform HES-DVMTM is a Hybrid Verification and Validation Platform for Hardware and Software developers of SoC and ASIC designs up to 144M ASIC gates. Utilizing

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Source URL: www.aldec.com

Language: English - Date: 2015-02-02 17:14:32
62Line One Sales Limited, The Quadrant, 99 Parkway Avenue, Sheffield, S9 4WG Tel: +1169 • Fax: +783 Email:  • Web: www.lineonesales.co.uk Leading the way with new pr

Line One Sales Limited, The Quadrant, 99 Parkway Avenue, Sheffield, S9 4WG Tel: +1169 • Fax: +783 Email: • Web: www.lineonesales.co.uk Leading the way with new pr

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Source URL: www.lineonesales.co.uk

Language: English - Date: 2014-03-28 07:52:35
63Project result  CT302 I Towards one European test solution [TOETS] A testing dilemma As semiconductor chip

Project result CT302 I Towards one European test solution [TOETS] A testing dilemma As semiconductor chip

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Source URL: www.aeneas-office.eu

Language: English - Date: 2014-07-21 10:33:01
64Food Vendor Application pgRoots N Blues N BBQ Festival Food Vendor Application Please read all information and requirements carefully before completing the vendor application. Vendor Application and $200 refunda

Food Vendor Application pgRoots N Blues N BBQ Festival Food Vendor Application Please read all information and requirements carefully before completing the vendor application. Vendor Application and $200 refunda

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Source URL: rootsnbluesnbbq.com

Language: English - Date: 2015-04-28 11:57:08
    65Yosys - A Free Verilog Synthesis Suite Clifford Wolf, Johann Glaser† Johannes Kepler University, Austria Institute for Integrated Circuits ,  †

    Yosys - A Free Verilog Synthesis Suite Clifford Wolf, Johann Glaser† Johannes Kepler University, Austria Institute for Integrated Circuits , †

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    Source URL: www.clifford.at

    Language: English - Date: 2013-10-11 16:34:33
    66Yosys Open SYnthesis Suite  Clifford Wolf (http://www.clifford.at/yosys/) Clifford Wolf http://www.clifford.at/yosys/

    Yosys Open SYnthesis Suite Clifford Wolf (http://www.clifford.at/yosys/) Clifford Wolf http://www.clifford.at/yosys/

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    Source URL: www.clifford.at

    Language: English - Date: 2015-02-09 07:25:30
    67Xilinx Training Course Listing  Effective April 1, 2015 II

    Xilinx Training Course Listing Effective April 1, 2015 II

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    Source URL: japan.xilinx.com

    Language: English - Date: 2015-04-14 15:20:39
    68OpenCores HDL modeling guidelines This document describes the OpenCores HDL modelling guidelines with some examples Brought to You By OpenCores

    OpenCores HDL modeling guidelines This document describes the OpenCores HDL modelling guidelines with some examples Brought to You By OpenCores

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    Source URL: cdn.opencores.org

    Language: English - Date: 2011-06-07 09:12:49
    69

    PDF Document

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    Source URL: www.aldec.com

    Language: English - Date: 2015-02-02 14:11:43
    70Yosys Manual Clifford Wolf Abstract Most of today’s digital design is done in HDL code (mostly Verilog or VHDL) and with the help of HDL synthesis tools.

    Yosys Manual Clifford Wolf Abstract Most of today’s digital design is done in HDL code (mostly Verilog or VHDL) and with the help of HDL synthesis tools.

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    Source URL: www.clifford.at

    Language: English - Date: 2015-02-09 07:25:28